VLSI Design Project Ideas

ECE 559/659 Spring 1998
Univ. of Masschusetts-Amherst

Projects:

1. Optimality of Certain Hybrid Adder Circuits

Adder circuits form the most basic component in any computing machine. Most of currently designed adders are of the hybrid type which combine several techniques for accelerating the carry propagation. Lynch and Swartzlander [1] have presented a hybrid adder which they call a Spanning Tree Carry Lookahead Adder. Later, Kantabutra [2] proposed a modification to the above, called RCLCSHA, which is an extension of the adder in [1]. It has been shown (in [3]) that Kantabutra's RCLCSHA is not optimal. Further improvements to the RCLCSHA hybrid Adder with respect to its speed of operation were presented in [3]. The goal of this project is to find an adder that is faster than the RCLCSHA hybrid Adder and demonstrate its optimality. The project involves identifying an optimal structure of MCCs (which are the basic elements in the RCLCSHA adder) to speed up the carry generation, designing several such MCC circuits and analyzing their performance.
References:
1. A Spanning Tree Carry Lookahead Adder, T. Lynch and E. E. Swartzlander, Jr. IEEE Transactions on Computers Vol. 41 No.8, August 1992.
2. A Recursive Carry-Lookahead/Carry-Select Hybrid Adder, V. Kantabutra, IEEE Transactions on Computers, Vol.42, No. 12, December 1993.
3. Study of Hybrid Adder Circuits, I. Koren, M. Olausson and S. Shirgurkar, technical draft report, Spring 1997, Dept. of ECE, University of Massachusetts, Amherst
For additional information please contact Shreedhar B. Shirgurkar, sshirgur@risky.ecs.umass.edu.

A public-key cryptosystem can be used to encrypt messages sent between two communicating parties so that an eavesdropper who overhears the encrypted messages will not be able to decode them. Each participant has both a public key (S_A) and a secret key (P_A). The public and secret keys for any participant are a "matched pair" in that they specify functions that are inverses of each other. That is,

M = SA(PA(M))
M = PA(SA(M))

for any message M. Transforming M successively with the two keys S_A and P_A, in either order, yields the message M back. In the RSA public-key cryptosystem, each key is a pair of integers, and the encryption operation to convert a message into ciphertext and back is modular exponentiation which can be performed using successive squaring. This project requires the design of a chip which takes a message and a key (two integers) as input, and performs modular exponentiation to produce the ciphertext. The decryption function is identical to the encryption function, so the chip will be used for both. The core of this design will be a modulo multiplier for large numbers whose details can be found in a paper by Takagi in IEEE Transactions on Computers, August 1992.
References:
1. Introduction to Algorithms, T. Cormen, C. Leiserson, and R. Rivest, McGraw Hill Publishers, 1991, pp. 834-837.

Lossless data compression provides a simple way to reduce the redundancy in data, however, the compression algorithm must be implemented in real time to achieve the necessary performance. This project will implement an architecture for the Lempel-Ziv data compression algorithm (or the LZW variant). Lempel-Ziv variants are commonly used in Unix "compress" and "zip" programs. The standard algorithm substitutes long substrings with single symbols that are stored in a dictionary. In this way, large amounts of redundancy can be removed from data. Since the FSM is fairly simple, testability may be considered in this design.
References:
1. A Universal Algorithm for Sequential Data Compression, J. Ziv and A Lempel, IEEE Trans. on Information Theory, vol IT-23, no. 3, May 1977, pp 337-343.

This project is similar (if not identical) to that in the ECE350 lab. You will be given a specification of the instruction set, instruction format, and a block diagram of the microprocessor; your task will be to design a microprocessor on a single chip. Since this design is already a familiar one, this project will require the use of design-for-test strategies.
References:
1. See the instructor for more information.

 

This project involves the design of either a finite impulse response (FIR) filter, or an infinite impulse response (IIR) filter. Signal flow graphs for these classes of filters can be found in any book on digital signal processing, but almost no knowledge of DSP is required to complete the project. The designs are composed of registers, adders, and constant multiplications. Since these designs are straightforward, design-for-test will be emphasized for this project.
References:
1. See the instructor for more information.