Description

This is a success design case in which Cadence tools are used in all over the design flow. The purpose of this design is to implement the Lempel-Ziv (77) data compress algorithm. Since there are lots of common between C-language and VHDL/Verilog behavioral description. We first developed a C program for the algorithm to guarantee its correctness. Comparing with other popular algorithm ( such as gzip, compress) we found the Lempel-Ziv(77) algorithm achieves a little bit worst compression ratio in most examples we investigated. But it is much simpler and easier to implemented in the IC chip. So this algorithm is good for the real-time compression, such as wireless communication.

Achievements and Results

C-program of Lempel-Ziv(77): Compress and Uncompress program. (need to be compiled).

HDL of Lempel-Ziv (77): VHDL verison.

We use Leapfrog to simulate the VHDL source code, then use Synergy** to do the synthesis and get the final result. The following is the gate-level schematic after synthesis.
 
 

Then we pass the gate level netlist to Verilog-XL and performed the simulation. Comparing the output waveform with the simulation of VHDL code, we found it match well although the timing is not exactly the same. We also did a fault simulation using Verifault. But the fault coverage is so attractive and we still need to improve the test pattern quality or increase the test patterns.

The final layout is finished by Cell-Ensemble. Unfortunately, we have no enough time to perform the layout verification using Dracula although that would be a good practice.