Cadence University Alliance Program Member
Introduction of 
tools
All the Cadence tools we are currently using is the
version of 97A.
In the class ECE 659 of Spring'98, we will mainly
use Cadence tools to do the projects/labs. Cadence Design Systems presents
both system level and chip level design solutions. In the course projects,
it is recommended that you use Cadence for the whole design flow. If you
use the academic tools or interchange different vendors' tools, you might
encounter lots of inconsistency problems between different design level.
Here we introduce some frequently used Cadence tools.
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Composer: this is the schematic entry tools. You can use the tools
to draw a schematic. After extract the netlist, you can use it as the input
of simulation tools.
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Verilog-XL: logic simulation tool. It can also perform some timing
checks during the simulation. The input of Verilog-XL is verilog format
file. The source code is either in behavioral level or register level.
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Verifault: fault simulation tool. Before designs are sent out to
the foundry, the fault simulation should be done in order to get a fault
coverage. It also gives you the information such as how to improve the
test patterns to get higher fault coverage.
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Leapfrog: VHDL simulator.
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Cell Ensemble: standard cell place/route tool. We will use the 2.0um
MOSIS standard cell library which is translated from the magic format.
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Virtuoso: Custom layout editor
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Dracula: layout verification tools. It does the LVS, DRC and sometimes
it is also used to extract the RC parameters.
The biggest issue when using the Cadence tools
is obtaining the proper libraries. We already invested a lot effort to
prepare a 2.0u MOSIS compatible library to support the whole top-down design
flow. And this library is suitable for the educational purpose whose basic
objective is to help students quickly learn the state-of-the-art design
tools and flow. Students are also encouraged to download and install new
libraries from their own ways. Figuring out yourself is one of the best
way to learn.
Value-added Items
-
Quick
setup of Cadence environments
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Design
Projects/Labs these projects are used in class ECE 659 of Spring 1998.
-
Design
flow: this top-down design flow is for VLSI digital desgin with Cadence
tools.
-
A
design example This example is derived from a previous course project.
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Standard
cell library is translated from MOSIS 2.0u library and it supports
logic synthesis, logic simulation, fault simulation and place/route.
More information about Cadence tools can be found:
Disclaimer
These pages mainly contain information that is related
to products produced by Cadence Design
Systems, Inc.
This is NOT a "Cadence Homepage".
Information is provided "as is" without warranty or
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using it on a copy of your data to be sure you understand what it does
and under your conditions. Keep your master intact until you are personally
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Last Updated: 10 Oct. 98
Contact information: Prof. Harris ( harris@ecs.umass.edu ).
Please send comments to Zhihong Zeng ( zzeng@ecs.umass.edu).
Cadence is a trademark of Cadence Design Systems, Inc.
555 River Oaks Parkway, San Jose, CA 95134.