Reconfigurable Computing Group         VPR for Virtex + JBits Interface

Table of Contents:
  • Introduction

  • Design Flow

  • Download and Installation

  • Tutorial of Tools:  (command script)

  • Technical Documentation

  • Reference

  • Limitations



    1.   Introduction

           VPR for Virtex and JBits Interface are CAD tools developed by RCG,Umass Amherst for the Fault Tolerant FPGA System. In this system, VPR for Virtex performs the task to pack, place and route the input design, JBits Interface reads the routed design to generate a configuring bitstream for Virtex[1] FPGA.

           VPR for Virtex are developed on the base of VPACK & VPR(Versatile Packing, Placement & Routing Tool)[2], which is an packing,  placement and routing tool developed by University of Toronto.  Compared with original VPR, VPR for Virtex can create an accurate routing graph for Virtex FPGA, which will guarantee routed design can be implemented on Virtex FPGA correctly.

          JBits Interface is a java tool developed on the base of JBits API (Application Programmable Interface)[3] provided by Xilinx.  With aids of JBits API, JBits Interface can generate configuring bitstream for Virtex FPGA directly based on the routed design from VPR for Virtex.

           The combination of those two tools can recover a faulty Virtex FPGA much faster than the Xilinx PAR(place and route) and Bitgen (bitstream generation) tool.

    2.    Design Flow

           By combining VPR for Virtex and JBits Interface, the design flow shown in figure 1 can pack, place and route the input design in Berkeley Logic Intermediate Format (blif), and generate a bitstream to configure Xilinx Virtex FPGA.

                               Figure 1. Design Flow

    Before you start evaluating the tool, please read the  Limitations and the DISCLAIMER

    3.    Download and Installation
      Installation Instructions:

    1. VPR for Virtex

    2. JBits Interface

    4.    Tutorial of Tools

    Part 1 -> VPR for Virtex

              Note: please remove all comments from samp.blif, also make sure logic gates has no more than 4 inputs, so each gate can be implemented by 4-input LUT in Xilinx FPGA.
                     1. Comment  "# LIB_DIR = -L/usr/operwin/lib";
                       Enable       "LIB_DIR = -L/usr/X11R6/lib";

                   2. Comment  "# X11_INCLUDE = -I/usr/openwin/include";
                       Enable       "X11_INCLUDE = -I/usr/X11R6/include";

    -nodisp Disable all graphics
     -route_chan_width 108  Tracks in routing channel of Virtex FPGA
    -nx  Number of columns of CLBs in target FPGA) 
    -ny Number of rows of CLBs in target FPGA

              Options determined by size of target FPGA (XCV100 or XCV300):
    XCV100 -nx 30  -ny 20
    XCV300 -nx 48  -ny 32

    -dm11: [ on | off ] Choose mode for dm11 board test or general case
    if "on", user must choose XCV100 size and provide a PAD file (sample) for dm11 board by option "-fix_pins  PAD file".
    -incremental : [ on | off ] Choose incremental re-route mode or route from scratch.
    Note: incremental on will set option -route_only automatically
    -num_faults: [ interger ] Number of faulty tracks found.
    a). If incremental is "on" and num_faults = 0, the faults will be read from text file "fault.dat".
    b). If incremental is "on" and num_faults > 0, the faults will be chosen randomly.
    -num_iters:   [ interger ] Number of iterations to test incremental re-route.

    Part 2 -> JBITS Interface

         Assuming you have already finished Part 1 and got the following files:

    1) Blif file: samp.blif  (sample)
    2) Netlist file:  (sample)
    3) Placement file: samp.p  (sample)
    4) Initial routing file: samp.r (sample)
    5) Updated routing file: samp.r3 (sample)

        "java  jbitspad  [options]" can generate a configuration bitstream.
           "java  xdlpad  [options]" can generate a XDL[4] file.
      Options for JBits interface:
    -dm11: [ on | off ] Choose dm11 board test or general case. Must be same as the option used for VPR for Virtex
    -place : [ on | off ] Choose whether to output the placement information or not, only valid for XDL output.
    -route:  [ on | off  ] Choose whether to output the routing information or not, only valid for XDL output.
    -dbg: [ on | off  ] Choose whether to output debug information or not.
    -incremental: [on | off ] Choose whether to create bitstream incrementally or from scratch. Must be same as the option used for VPR
    [XCV100 | XCV300]
    Choose target device: XCV100 or XCV300, must be compatiable with size options for VPR

    5.  Technical Documentation

          Following documentation is for users who needs more details about our tools. And it's strongly recommended to read the following references first if users are not familiar with Virtex, VPR orJBits.


    [1.]  Virtex Data Sheet, Xilinx Corporation,1998.
    [2.]  V.Betz and J.Rose.VPR:A New Packing,Placement,and Routing Tool for FPGA Research. In Proceedings,Field Programmable Logic,Seventh International Workshop ,Oxford,UK,Sept.1997.
    [3.]  JBits 2.8 SDK for Virtex. Xilinx Corporation,1999.
    [4.]  XDL (Xilinx Design Language) Version 1.4, Xilinx Corporation,1998.

    Contact Authors

    Weifeng Xu
    Reconfigurable Computing Group
    KEB 302
    University of Massachusetts
    Amherst MA 01002
    Email :

    Vibhor Garg

    Ramaswamy Ramaswamy

    Carlos Bedoya