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Weifeng
Xu
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I received my M.S.
and B.S. from the Department of Electrical Engineering, Fudan
University,
Shanghai, P.R.China
- Digital system design and prototyping using FPGAs.
- Compiler-assisted fault tolerance for FPGAs.
- Compiler optimization for VLIW processors.
| Research in Reconfigurable Computing Group,
UMass Amherst |
| Teaching
Assistant Experience |
- W.Xu and R.Tessier, “Tetris-XL: A Performance-Driven Spill Reduction Technique for Embedded VLIW
Processors,” submitted to ACM Transactions on Architecture and Code Optimization.
- W.Xu and R.Tessier, "Tetris: A New Register Pressure Control Technique for VLIW Processors," in ACM Conference on Languages, Compilers, and Tools for Embedded Systems,
pp. 113-122, June 2007.
(pdf)
- P.Menon, W.Xu and R.Tessier, "Design-Specific Path Delay Testing in Lookup Table-based FPGAs," IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 25, no. 5, pp. 867-877, May 2006.
(pdf)
- R.Tessier, D.Jasinski, A.Maheshwari, A.Natarajan, W.Xu and W. Burleson,
"An Energy-Aware Active Smart Card," IEEE Transactions on VLSI Systems, vol. 13, no. 10, pp. 1190-1199, October 2005.
(pdf)
- W.Xu, R.Ramanarayanan and R.Tessier, "Adaptive Fault Recovery for Networked Reconfigurable Systems," in IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 143-153, April 2003.
(pdf)