Designing and simulating a NAND gate
TaskDevelop a 2-input nand gate which has the capability to drive 5 minimum size CMOS inverters and 2fF of lumped wiring cap. The propagation delay must be less then 80ps. Use 50ps rise and fall times for the inputs. The gate must also fit our standard cell library; height = 100 lambda with 20 lambda rails for vdd and ground. Minimize the width of the cell. You may only use M1 and M2 layers. The inputs and output must be accessible from the top of the cell (VDD side) in metal 2. |