Logic Design
Given a 2-input nand gate with inputs A and B, the truth table looks like:
|
A\B |
0 |
1 |
|
0 |
1 |
1 |
|
1 |
1 |
0 |
Since only logic ones as inputs result in a zero output the schematic has to look like:
There
are two PMOS in parallel serving as the pullup network and two NMOS
in series as the pulldown network.
Simulating the output using IRSIM results in the following picture:
As you can see the circuit utilizing two PMOS and two NMOS is a functioning nand gate.