Circuit Design
Since the fan-out of the nand gate is a design goal the calculation of the size of the transistors must be done with it in mind. The total load capacitance has to be calculated. It consists of the wiring capacitance (50fF) and the input capacitance of the following 32 minimum-sized inverter gates. Taking the sizes of the MOSFETs
and plugging them into the equation
you get 0.558fF for each NMOS and 1,116fF for each PMOS. This results in a total load capacitance of 103,568fF. Other capacitances can be neglected since they are really small compared to this.
To calculate the propagation delay you can use the following equation:
The difference between high and low input voltage can be assumed to be the power voltage. Taking into account sub-micron effects (velocity saturation) you have to use the following equation:
The worst case low to high transistion takes place when only one inputs is set low. This means that only one PMOS is able to source current. Thus the equation to be used is:
The worst case high to low transistion takes place when both inputs are set high. This has the same effect as sourcing the current through a transistor with twice the length. So you have the equation looks like:
Plugging in
you get
.Simulating the circiut with these dimensions you get propagation delay of 226 ps for a high to low and 255 ps for a low to high transistion. So it is possible to reduce the size of the transistors further and increase the propagation delay. Setting the ratio of the minimum width of the transistors and the calculated width the same as the ratio of 300ps and the simulated width you get the new widths:
Simulation shows that it is not possible to reduce the size any
further without missing the design goal. The final Hspice input file is: sch.cir
The Hspice output looks like:
The
worst case high to low transistion has a propagation delay of 287 ps
and the worst case low to high transistion has a propagation delay of
298 ps.