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LAB4

Ultra Low-Power Fault Detecting Counter

Introduction

With the advent of miniaturised design sizes and portable system desing, it has become imperative to design systems that have very low power consumption. That is systems that can be supported by an on-board power supply (battery).This in turn led designers to use new adiabatic logic styles rather than conventional static CMOS for their design. Unlike conventional static CMOS, where the energy stored in the node capacitance is discharged to ground, the adiabatic logic families use the concept of recycling them. Thus achieving low energy dissipation.  
In this lab a counter is implemented using a mixuture of two adiabatic styles of design namely 1) Clocked CMOS adiabatic logic (CAL) [1] and 2) Pass-transistor adiabatic logic (PAL) [2]. Double modular redundancy is used to made the counter fault detecting. The implementation of the counter is discussed in the following sections. 

Counter Implementation

This section outlines the procedure to design a 4-bit binary counter using D flip-flops. The input equations for the D flip-flops are obtained directly form the next state values as shown below. 

    Input equations.
The Block diagram of the counter implemented with the above input equations is shown below.

Working of PAL family

The D flip-flop used in the counter is designed using the clocked CMOS adiabatic logic (CAL). The schematic of the latch is shown below. 

In the above circuit when both Clk and In are high then the output node goes to zero. This turn on transistor M7 and so OUTB follows the power clock. The cross coupled CMOS inverters provide the momory function. When CLK is one then the output is the complement if the input. This value is held until the next clock cycle. Thus the above circuit acts as a latch.
The adiabatic schematics for the XOR and the AND gates are shown below. 

schematics for 2-input XOR gate.  

schematics for 2-input AND gate.  

simulations

The first step in the design of the 4 bit adiabatic counter is to design one bit-slice.This bit slice can then be arrayed four times to obtain the 4 bit counter. This stage by stage development eliminates the possiblities of error right from the early stages of design. The schematics, spice simulation of schematics, layout and spice simulation of the layout for one bit slice of the counter are listed below.

First Bit-Slice simulations
1. Schematic of the first bit-slice.  
2. Spice simulation of schematic.  
3. Layout of the first bit-slice  
4. Spice simulation of layout.  

Four Bit Counter Simulations
1. Schematic of 4 bit counter.  
2. Spice simulation of schematic.  
3. Layout of a 4-bit Adiabatic Counter .  
4. Spice simulation of layout .  

Fault Detection

Fault detection in this system is provided by implementing double modular redundancy. The counter is replicated twice and an error detection ciruit (XOR Gate) at the maximum switching node namely Q0 is included. Whenever there is a difference between Q0 from the first counter and Q0 from the second counter an error signal goes high. This enables to detect errors in the counter. Although this is not fully error detecting it is reasonable to expect more errors at the node which has the maximum switching. The block diagram, layout and spice simulation of such an error detecting counter is shown below. 
1. Block Diagram of fault detecting Counter.  
2. Layout of fault detecting Counter.  
3. spice simulation of fault detecting counter.  

Conclusion

Two conventional four-bit CMOS counters dissipates 137.7 micro watts. The same counters when designed in the adiabatic style described above with the same clock frequencies dissipates only 21.42 micro watts. Hence it is concluded that there is 84.4 % of power savings by using the above mentioned adiabatic style of design.

Future Work

1. The same system can be designed to be error correcting.
2. Insted of using a binary counter a gray counter which has very less switching can be used to reduce powere consumptions further.

References

1.   Clocked CMOS Adiabatic Logic with Integrated Single-phase Power-clock Supply - Dragan Maksimovic, Vojin G. Oklobdzija and K. Wayne Current : IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 4, August 2000.
2.    Pass-Transistor Adiabatic Logic using single power-clock suppy - Vojin G. Oklobdzija, Dragan Maksimovic and Fengcheng Lin : IEEE transactions on circuit and systems - II:Analog and digital signal processing, Vol. 44, No. 10, October 1997. 
  
   
    
  
 
 
 
 
 
 
 
  

  
Send comments to: Santosh sperumba@ecs.umass.edu