ECE 658 - VLSI Design - Lab 1
Design of a NAND Gate
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  1. NAND Truth Table

  2. NAND Schematic



  3. Schematic Logic Simulation



  4. Hand Calculations for Device Sizes and Power

  5. Simulated vs. Hand-Calculated Delays

  6. Schematic Performance Verification



  7. NAND Layout



  8. Layout Functional Simulation



  9. Layout Performance Verification