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<title>VLSI Lab
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ECE 658 - VLSI Design - Lab 4<br>
4x4 multiplier Gate<br>
STEHPEN LEBLANC<br>
12/15/05<br>
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<h3><li>4x4 Schematic </li></h3>
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As shown below, The circuit is made up of 16 AND gates and 12 Full adders<br>
Some of the full adders have had an input put to ground so that it acts as a half adder.<br>
While the use of half adders would be cheaper over less area designing them was<br>
Not required as its much easier to modify the full adder.<br>
<img src="">4x4sch.bmp<br>
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<h3><li>
Schematic</li></h3>
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<img src=""><br>
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<h3><li>Schematic
Logic Simulation</li></h3>
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<img src="analyzer.bmp"><br>
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<h3><li>Hand
Calculations for Device Sizes and Power</li></h3>
<img src=""><br>
<h3><li>Schematic
Performance Verification</li></h3>
<img src=""><br>
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<h3><li>NAND
Layout</li></h3>
<img src=""><br>
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<h3><li>Layout
Functional Simulation</li></h3>
<img src="template_files/layout_irsim.htm"><br>
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<h3><li>Layout
Performance Verification</li></h3>
<img src="template_files/layout_waves.htm"><br>
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