Department of Electrical and Computer Engineering
308 Knowles Engineering Building
University of Massachusetts
Amherst, MA 01003
Phone : (413) 545-0831
Email : rramaswa [AT] ecs [DOT] umass [DOT] edu
Curriculum Vitae : PDFtext
Relevant Projects and Research
Currently, I am a member of the Network Systems
Laboratory headed by Prof. Tilman Wolf. My research work focuses on
system
design using network processors and the applications of such systems in
the
areas of network security and measurement. Specific areas of research
include:
Performance analysis and
characterization of network
processor workloads [PacketBench]
Application mapping to
network processor architectures
Performance modeling of
network processors
Performance and privacy
issues in network processor based measurement systems
High speed co-verification interface between
SystemC
and a Mentor Graphics VStation emulator.
Developed an
interface
between software models written in SystemC
and a Mentor Graphics VStation
logic emulator for my
Master's
thesis. A SystemC model of a testbench communicates with a Verilog gate
level
DUT running on the emulator. Communication between both verification
domains
is transaction based. This offers much higher performance over software
based
simulation approaches or simulation accelerators. The interface was
used to
verify the functionality of a system-on-a-chip design consisting of a
Reed
Solomon coder (obtained from Texas
Instruments)
and a Viterbi coder. The work is currently being extended to support
devices
that communicate via the PCI-X bus, using a transactor developed at
UMass
for the PCI-X protocol. This project was done when I used to work in
the Reconfigurable
Computing Group under Prof.
Russell Tessier.
Programmable Interconnect Switch for Tiled
Logic Architectures
(TLA)
The switch
enables
inter tile communication in a TLA array, featuring static routing and
architectural
scalability. The major blocks designed are the RAM, decoder, crossbar
and
some control logic. The various phases of the project include
behavioural
simulation,circuit design and layout. This design was implemented in
1.2u
technology and has been scaled down to newer technologies.
More information on related projects can be
found here.
A Java based tool
for
dynamic modification of an FPGA configuration bitstream. This tool
takes in
an existing configuration bitstream and a new circuit description,
generates
place and route information and creates a new configuration bitstream.
This
tool is expected to be used for network based fault diagnosis and
recovery.
Custom design of a
cellular
array Galois field multiplier for finite field multiplication in 1.2u
technology
utilizing pass transistor logic. Performed circuit design, behavioral
simulation
and layout.
Ramaswamy, R., and Wolf, T.:
"High-Speed Prefix-Preserving IP Address Anonymization for Passive Measurement Systems",
accepted/to appear in IEEE/ACM Transactions on Networking. (also available as
UMass ECE Technical Report TR-06-CSE-01)
Tessier, R., Swaminathan S., Ramaswamy R.,
Goeckel D., and Burleson W.: "A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder",
in IEEE Transactions on VLSI Systems, Volume 13, Number 4, pp. 484-488,
April 2005.(PDF)
Ramaswamy, R., Weng,
N., Wolf, T.: "Application Analysis and Resource Mapping for
Heterogeneous Network Processor Architectures", in Network Processor Design:
Issues and Practices, Volume 3, Mark A. Franklin, Patrick Crowley, Haldun Hadimioglu,
and Peter Z. Onufryk, Eds., chapter 13, pp. 277-306. Morgan Kaufmann Publishers, Feb. 2005.
(LINK)
Conferences and Workshops
Wolf, T., You, S.,
Ramaswamy, R.: "Transparent TCP Acceleration Through Network Processing", in Proc. of IEEE
Global Communications Conference (GLOBECOM), St. Louis, MO, November 2005. (PDF)
Ramaswamy, R., Weng,
N., Wolf, T.: "Analysis of Network Processing Workloads", in Proc. of IEEE
International Symposium on Performance Analysis of Systems and Software (ISPASS),
Austin, TX, March 2005. (PDF)
Ramaswamy, R., Weng,
N., Wolf, T.: "Characterizing Network Processing Delay", in Proc.
of IEEE Global Communications Conference (GLOBECOM), Dallas, TX, November 2004.
(PDF)
Ramaswamy, R., Weng,
N., Wolf, T.: "Application Analysis and Resource Mapping for
Heterogeneous Network Processor Architectures", in Proc. of Third
Network Processor Workshop in conjunction with Tenth
International Symposium on High Performance Computer Architecture (HPCA-10),
Madrid, Spain, February, 2004. (PDF)
Ramaswamy, R., Wolf,
T.:"PacketBench: A Tool for Workload Characterization of Network
Processing",
in Proc. of 6th IEEE Annual Workshop on Workload Characterization
(WWC-6),
pp. 42-50, Austin, TX, October 2003. (PDF)
Ramaswamy, R., Weng,
N.,
Wolf, T.: "Considering Processing Cost in Network Simulations",
in Proc. of Workshop on Models, Methods and Tools for Reproducible
Network Research (MoMeTools) in conjunction with ACM SIGCOMM,
pp. 47-56, Karlsruhe, Germany, August 2003. (PDF)
Ramaswamy, R. and
Tessier,
R.: "The Integration of SystemC and Hardware-assisted Verification",
in Proc. of the 12th International Conference on
Field-Programmable
Logic and Applications, Montpelier, France, September 2002.
(PDF)
Abstracts and Posters
Ramaswamy, R., Weng,
N., Wolf, T.: "A Network Processor Based Passive Measurement Node", in Proc. of
Passive and Active Measurement Workshop (PAM), Boston, MA, March
2005. (Extended Abstract)(Poster)
Ramaswamy, R., Weng,
N., Wolf, T.: "An IXA-Based Network Measurement Node", in Proc. of Intel IXA University Summit, Hudson, MA, September 2004. (PDF)
Ramaswamy, R., Weng,
N., Wolf, T.: "Workloand Analysis for Network Processor Design", in Boston
Area Computer Architecture Workshop (BARC2004), Boston, MA, January
2004. (PDF)
Other Stuff
Ramaswamy, R.: "Integration
of SystemC with an Ikos VirtuaLogic Emulator", Master's thesis,
Department
of Electrical and Computer Engineering, University of Massachusetts,
Amherst,
September 2001. (PDF)
