I.) Proposal
II). Sub-circuit Design & Testing
A.) Sample-and-Hold
Since the focus of this design project was on the
designing and testing of the A/D circuitry and not the design of the
sample-and-hold
circuit I used a very simple charge storage sample-and-hold circuit. This is
simply an analog signal applied to a pass transistor, who's
output is a capacitor. When the pass gate is on the capacitor charges up to the
analog value "tracing" the analog input. When the pass gate
is turned off the last value of the analog input is stored on the output
capacitor and is a static voltage. This static voltage is compared to the
reference voltages at the comparator inputs. The schematic, layout, and HSPICE
simulation results for both can be found in the figures below.
The power consumption for the sample and hold circuit was; Pdyn = 7.348e-08 W
and Pstat = 7.849e-26 W. Clearly not a factor in the
overall power consumption of the A/D.
Schematic Layout
From the HSPICE simulations above the biggest draw back of this simplistic
form of a sample-and-hold circuit can be seen. This design
suffers from charge injection and clock feedthrough, which cause the stored
voltage on the output capacitor to jump higher than the analog
value when the pass gate turns off. There are many methods of correcting these
problems discussed in a paper by Joyce Cheuk Wai
Wong.
B.) Reference Voltages
The easiest way to produce the 16 voltage reference levels
between two voltage rails
would be with a resistor tree. However,
this produces
very large static power consumption. I built a resistor tree using 50Ω
resistors and tested it using HSPICE for static power consumption. The result
was Pstat=3.125e-02
W.
To produce 16 voltage references between 0 and +2.5V I used a
tree of equally sized (L=360,W=360) PMOS devices, whose gates
were connected together to -2.5V. By doing this the devices were always on
and their Ron (equivalent on resistance) divided the +2.5V just
as a resistor tree does.
Similar to the 50Ω resistor tree, I used HSPICE to measure the static power
consumption of the transistor tree.
The power consumption was much less for this method of producing reference
voltages; Pstat = 3.670e-05 W. This an improvement of
approximately 10e2 over that of the consumption of the resistor tree network
even when the PMOS devices are always on. It is even
possible to further reduce static power consumption by controlling the
common gate of the PMOS devices with a clock, turning them off
when the reference voltage level is not needed by the comparators. The
schematic, layout, and HSPICE simulation results for both can be
found in the figures below.
Schematic Layout
Comparing the HSPICE results of the schematic
and layout it can be seen that the voltage levels produced are not exactly the
same, but are
in the correct order. The design was such that the linearity between voltage
levels was held not the
monotonously nature of a voltage divider
as described above.
C.) Comparator
The next major section of the A/D design is the
comparator. The sampled analog input and one of the 16 reference voltages is input
to each comparator. The comparator used performs a greater than function. When
Vin < Vref the comparator output Q is Low and when
Vin > Vref Q is HIGH. This comparison is valid when the comparator control
signals sample and sample are HIGH and LOW respectively.
The first time sample is HIGH the reference and input voltages are sampled,
during the next period that sample is LOW the values are
compared, and finally during the following HIGH pulse of sample the Q output of
the comparator is updated.
I felt it important to maximize the accuracy of the
comparator to perform this greater than comparison and thus choose values of
series
capacitance accordingly. By trial and error a series capacitance of 200 fF was
chosen. With this value a difference of 10 mV between the
sampled analog and reference voltage could be detected. For the layout this
capacitance was added to the .spice file between the appropriate node. This was
done assuming chip capacitors could be added in the fabrication process that
would be used to produce the device. The comparator PMOS and NMOS devices were
sized to be 2/1.5 (L/W) as suggested by the Flash A/D section in
"
? ". The comparator was the major contributor to the
power consumption of the A/D, having Pdyn=7.890e-04 W and Pstat=2.834e-04 W. The
schematic, layout, and HSPICE simulation results for both can be found in the
figures below.
Schematic
Layout
From the HSPICE results it can be seen that an input signal was used to check
that the Q output of the comparator had the accuracy of 10mV
for which it was designed. This was done by trial and error for the schematic
and verified with the layout simulation. By observation of both
HSPICE results it can also be seen that the comparator is operating correctly.
D.) NOR Gate
The output of the comparators is a "thermometer" code, which has to be
converted to a binary number. This is done with NOR gates and
a PLA-style decoder. The 3-input NOR gates are connected to the comparator
outputs in a manner to search for a 011 code. In other words
checks for a low Q output from the comparator above and a low
Q output of the
current and comparator below. This
code will appear
at the input of only one of the NOR
gates each clock cycle, signifying which line of the PLA to activate. The power
consumption of one NOR
gate was Pdyn=8.653e-05 W and Pstat=4.504e-08 W. The NOR gate truth table, schematic,
layout, IRSIM, and HSPICE results can be
found in the figures below.
NOR Gate Truth Table
Inputs Outputs Q above Qbar Qbar below 0 0 0 1 X X X 0
Schematic Layout
From the IRSIM results above the NOR gate performed the correct logic
operation. From the HSPICE results the maximum propagation
delay from a "true" input to a logic 1 output is negligible; approximately .2ns.
E.) PLA
The operation of the PLA is simple. The output of each NOR
gate is tied to
one line of the PLA grid via an NMOS devices. Every line has a
different binary code laid out by the NMOS devices. This binary code is the
output of the PLA and the Flash A/D. The power consumption for
the PLA was Pdyn=3.482e-04 W and Pstat=9.181e-08 W. The PLA schematic, layout, IRSIM,
and HSPICE results can be found in the figures below.
Schematic
Layout
From the IRSIM results above the PLA decoder performed the correct logic
operation. From the HSPICE results the maximum propagation
delay from an NMOS in the PLA pull down network turning on till a logic 1 is
seen at the PLA output is negligible; approximately .25ns.
III.) Complete A/D Design and Testing
Each subsection of the A/D design was implemented in
schematic placing symbols for each subsection in a top level design. The digital
output of the sample and hold circuitry was connected to one input on each of
the 16 comparator circuits. The other input coming from the appropriate
reference level of the PMOS reference voltage tree. The Q and
Q outputs of the comparators
driving the "thermometer" decoder (NOR gate and PLA). The A/D was tested using
HSPICE by applying a slowly increasing ramp function from 0 to 2.5V and verifying a
steady count from 0 to 15 by the A/D.
Testing in this method yielded a counting of the A/D that was
very sporadic. Knowing that my sample-and-hold circuit was far from ideal I
removed the sample-and-hold circuit from the schematic and directly applied to
the comparators a
signal which represented a cleaner sample-and-hold output. I felt this
adjustment was justifiable since I understand the limitations of my simplistic
sample-and-hold circuit and that the problems it faces can be corrected by
methods discussed in the referenced paper. It can be seen in the HSPICE output
file below this was successful and the A/D counted as intended. The power
consumption of the A/D was; Pdyn=2.916e-03 W and Pstat=2.309e-03 W. Most of this
is consumed by the 16 comparators since the rest of the A/D's subsections draw
fairly little. As far as the total design is concerned a power draw of
approximately 3 mA is very good. The original intent of this lab, as described
in the proposal above, was to design a Flash A/D that had low power consumption.
This type of device is crucial in portable communications devices such as cell
phones where there is a limited power supply. In comparison the complete A/D
design using the PMOS reference voltage tree uses 10x less power than just the
resistor tree alone. Thus a significant savings in the power consumption was
achieved without loosing any functionality of the A/D.
Although a layout was designed, tested, and verified for
each sub-circuit of the A/D design I couldn't get the complete A/D design to
simulate with HSPICE. Although there were no DRC errors, upon extraction the
tool failed due to the complexity of the total geometry. I worked on correcting
this problem for several weeks without any significant progress. After reviewing
the specific goals of my proposal and discussing with fellow classmates that
didn't do a layout for their lab 4 project, I decided that what I had tested
and verified with the complete A/D schematic and the individual sub-circuit
layout's was sufficient for meeting my goals for this lab. The 4-bit Flash A/D
schematic and HSPICE results can be found in the figures below along with the
complete A/D layout.
Schematic Layout
IV.) References
1.) Joyce Cheuk Wai Wong. CMOS Sample-and-Hold Circuits. 2001
2.) (?) Chapter 9.4 regarding Flash A/D supplied by Professor Burleson
3.) Voghell, J-C., et al. Programmable Current Sources Dedicated to Implantable Microstimulators
