Objective: To design a 2 input CMOS NAND gate using quarter micron technology.

1. NAND Truth Table

Inputs		Output
A	B	C
0	0	1
0	1	1
1	0	1
1	1	0

Above is the standard truth table for the NAND gate. The output (C) is always 1 except when both inputs A and B are 1, in which case the output is 0. This can be expressed in boolean as .

2. NAND Schematic



The above schematic was arrived at by using simple circuit theory. Since the circuit needs to be a 1 at all times except when both inputs are 1, two PMOS devices were used in parallel to assure that the circuit would be charging as long as at least one input, A or B, was not 1. When both inputs are 1, both NMOS transistors are on and discharging will take place. Note that the above schematic has the Wn(min) and Wp(min).

3. Simulator Output

The simulator output shown below demonstrates the correct implementation of the NAND gate truth table. i.e. The output always 1, unless both inputs A and B are 1, in which case the output is 0.



4. Hand Calculations

further details > Hand Calculations of Wn, Wp and Power

5 and 6. Final Design of NAND Gate

further details > Determining Wn and Wp



The Schematic above includes the final Wn and Wp and the load capacitance from the hand calculations. It is important to note that to have a balanced circuit Wp ~ 3*Wn(min), to make up for the difference in mobility between electrons and holes. In this case the width of each transistor is 3.48 μm, since the NMOS transistors are in series then the Wn is seen as approximately 1.7 μm, which would mean that to have a balanced circuit Wp should be approximately 5 μm. Since the PMOS transistors are in parallel then both PMOS transistors should have approximately 5 μm widths. In this case the circuit is not fully balanced because the PMOS transistors are not exactly 3*Wn, which would explain the slight difference in tpHL and tpLH. However the true ratio between holes and electrons is approximately 2.86 (275/96), in this design the true PMOS/NMOS ratio is 2.76 which is actually closer to 2.86 than 3.0 is. Of course, this becomes an argument over semantics because both are within the tolerance of most processes. Note that the capacitor from the hand calculations is located in the schematic, instead of the *.spice file as was shown in the nor example

Below is the HSpice awaves simulation plots showing the tpHL and tpLH for the worst case transitions. The worse case transitions were determined to be when [A=B=0 and A,B move to 1], and when [A=B=1 and B moves to 0]. This makes sense using circuit theory and was discussed in the RCN text, figure 6.9 pg. 244.



The HSpice Simulation File (nand.mt0) is shown below
where pstatic is the static power, pavghl and pavglh is the average power from the high to low and low to high transitions, and tphl and tplh are the time constants for the high to low and low to high transitions, respectively.
pavghl and pavlh were measured at the transitions, while pstatic was measured when no switching in the circuit was taking place (when both A=B=0, for example)

$DATA1 SOURCE='HSPICE' VERSION='    20'

.TITLE '***nand gate'

 pstatic pavghl pavglh tphl tplh temper alter#

  1.540e-10  5.071e-04  5.179e-04  2.522e-10  2.655e-10   25.0000    1.0000

A table summarizing the simulation results is shown below:

Figure of Merit	Hand Calculations	Simulated (w/ modified Wn, Wp)
tphl	300	252 ps
tplh	300	266 ps
tp	300	259 ps
Pstatic	~ 4.176 E-10 W	1.54E-10 W
Pdynamic	3.47 mW	0.51 mW

As can be seen in the above table each parameter exceeds the spec.  The static power which was calculated using the final Wn and Wp was within the range calculated. The dynamic power was quite smaller than the hand calculations, however, the model numbers used in the hand calculations were not accurate making this comparison mute.

7. Layout of NAND gate

The layout implementation of the two input NAND gate is shown below. The requirements for the layout were that vdd and ground have 20λ high rails, and that the total height of the NAND gate be a maximum of 140λ. In our case λ = 0.125 μm (since our technology is 0.25 μm) Therefore the total height of the NAND gate should not exceed 140*0.125 = 17.5 μm. In this layout the total height (measured from the top of the input/output (metal2) to the bottom of ground (metal1) was 16.32 μm, with a width of 4.98 μm, which is the minimum width (if we want to maintain an good amount of ohmic contact provided by ptap and ntap). The top of the input/output (metal2) should be counted because that is also part of the process, starting the measurement at the top of vdd would not be correct from a process standpoint. Also as can be seen from the picture only metal1 and metal2 were used.

 

A zoomed in view of the layout is shown below. The picture shows the input/output paths and the vdd and gnd connection/paths as well some of the via connections.



8. Layout functionality

The functionality of the layout is shown below, it was simulated with IRSIM after using the lo2sim script.



The functionality can also be shown using HSpice, that is shown below, notice the capacitance effects on the logic
functionality.



As can be seen in the above two pictures, the logic functionality is verified for this layout.

9. Performance of NAND layout

Below is the HSpice awaves plot of the two worst case transitions. The values of the low to high and high to low time constants can be seen to be below the 300 ps max. Also included below the plots is the text of the nand.mt0 file, which includes the powers of this layout.

$DATA1 SOURCE='HSPICE' VERSION='    20'

.TITLE '***nand gate'

 pstatic pavghl pavglh tphl tplh temper alter#

  1.540e-10  5.091e-04  5.015e-04  2.527e-10  2.578e-10   25.0000    1.0000

10. Summary

The lab1 objective of designing a quarter micron 2 input CMOS NAND gate was accomplished. The propagation delay was 256ps which is below 300ps, the circuit was also well balanced as can be seen by the time constants in the table below. This design can drive 32 min size CMOS inverters (Wn=0.36um, Wp=1.08um) and 100fF of lumped wiring cap.

The layout of the NAND gate has 20 lambda high rails in metal1 for vdd and gnd and the total layout fits the standard cell library height of 140 lambda, in this case the total height was approximately 130.5 lambda. The width of the NAND gate is approximately 40 lambda. Only metal1 and metal2 were used to implement the layout and all inputs and the output can be accessed from the "top" of the cell, in metal2.

The correlation between the schematic and layout HSpice simulation is shown in the table shown below:

Figure of Merit	Schematic	Layout
tpHL	252 ps	253 ps
tpLH	266 ps	258 ps
tp	259 ps	256 ps
Pstatic	1.54E-10 W	1.54E-10 W
Pdynamic	0.513 mW	0.505 mW

As can be seen above the correlation is quite good. The time constants are also well balanced and under the 300 ps requirement. The static power remained the same, while the dynamic power was was also well correlated between the schematic and layout.

Miguel Alvarado; Fall 2004