ECE 658 ( VLSI Design Principles ) Lab #1

Design and Simulation of A Two Input CMOS NAND Gate

Submitter: Hui Zhu ( huizhu@ecs.umass.edu )

Date: 10/03/2001

Objective  

Design a CMOS layout for a 2-input nor gate. And it should reach the following system requirement:

• The capability to drive 32 minimum size CMOS inverters (Wn=.3um, Wp=.6um) and 50fF of lumped wiring cap

• The propagation delay must be less then 300ps (Use 50ps rise and fall times for the inputs)

• The gate must also fit our standard cell library; height = 100 lambda with 20lambda rails for vdd and ground

• Minimize the width of the cell

• Only use M1 and M2 layers

• The inputs and output must be accessible from the top of the cell (VDD side) in metal 2

I. System Design:

       Given:  A two-input NAND Gate:

II. Logic Design:

The schematic of the two input CMOS NAND gate includes two parallel pmos transistors and two series nmos transistors. As long as an input has a LOW input, one of the two pmos transistors turns on while one of the two series transistors cuts off. The output port begins to charge and has a HIGH output.

The simulation output is done by IRSIM and the logical function of NAND Gate is thus verified.

III. Circuit Design:

Hand Calculation and Assumptions:

1. The load of the gates can be approximated calculated by the following:

C_g = (Number of Gates)*(Cap + Can) = N*(C_ox*W_p*L_p +C_ox*W_n*L_n)

C_g = 32*(9.3fF/um²*.3um*.2um+ 9.3fF/um²*.6um*.2um) = 53.568 fF

Cw = 50 fF

C_L= C_w + C_g = 50fF + 53.568fF = 103.568 fF

2. In sub-micron technology, the I_D is increasing proportional to the (V_GS - V_T). Page54 in the textbook gives the following formula to calculate the current:

I_D = k v _sat C_ox W ( V_GS - V_T ) for V_DS>=V_DSAT (saturated region) 

From Page134, we have the formula for the propagation delay computation:

t_p = C_L*(V_OH - V_OL) / 2 / | I_av |

For the worst case t_PLH, only one pmos on,  therefore, 

t_PHL =C_L * V_dd / ( K_p * W_p * ( V_DD - | V_Tp | ) )

t_PLH =C_L * V_dd / ( ( K_n / 2 )* W_n * ( V_DD - | V_Tn | ) )

3. Given hand calculation parameters:

 Hand calculation results for t_P=300ps: (Ln = Lp =200 nm)

Wp = 4.28 um

Wn = 3.23 um

Hand Calculation vs. Simulation Results: 

Since the worst case occurs when:  For t_PHL,  the worst case occurs when the inputs change from (0, 0) to (1,1)

                                                                          For t_PLH, the worst case occurs when the inputs change from (1,1) to (1,0) or from (1,1) to (0,1)

Therefore, if I got the worst tphl and tplh smaller than 300ps, the delay time will definitely with in the 300ps. And all my following results are in the worst case.

You may see the t_PHL & t_PLH clearly from the  waveform of original size of Nand Gate. You may also look the enlarged waveform for tpHL and waveform for tpLH.

NAND Gate Size Modification:

From simulation, we could see that tp is far away from 300ps, that means we have a lot of space to decrease the Wp and Wn. Here lists my simulation results:

I finally choose the size as following:

Wp = 1.8 um

Wn = 1.6 um

The HSPICE File is extracted from the schematic, running HSPICE and AWAVES we can get the t_PHL and t_PLH , please refer to the waveform for the tpHL and tpLH. Also the logical function is verified by the IRSIM.

IV. Layout Design:

• The Cadence (layout editor) is used to draw the Layout 2-input NAND gate with the modified size. 

• Verify the functionality of the layout using IRSIM. Here is the Simulation Result. 

• HSPICE is used to test the performance of system. A HSPICE file was generated after the extraction, and the  waveform for tpHL & waveform for tpLH  clearly indicated the tphl and tplh which are obtained from point to point measurement in AWAVES display window. 

• The dynamic and static power of the system: 

  • P_static = I_leakage * V_dd

  • P_dynamic = C_L * V_dd² * f

  • From the definition of the static power, we know that for NAND GATE, the power can be calculated when the 2 inputs are both 0, and theoriclly it should be 0, but since there are some current leakage, we may still get some small power. And it is calculated in the hspice file.

  • For the dynamic power consumption, it is due to the load capacitance CL, it will charge and discharge if the output changes. The average dynamic power consumption in a period is calculated by hspice.   

  • Here is the nand2md.mt0 file which shows the dynamic and static power:

$DATA1 SOURCE='HSPICE' VERSION=' 20'
.TITLE ' '
pavghl pavglh dynamic static temper alter#
9.700e-05 9.683e-05 9.692e-05 1.214e-11 25.0000 1.0000

• Summary: For 2-input NAND GATE I designed, it has the following characteristics (Ln=Lp=0.2uM)

Conclusion

In this lab, a 2-input NAND gate is successfully designed on the base of .18um technology. The logical function of NAND gate is verified by the IRSIM, and the layout is drawn by the Cadence. The HSPICE files are extracted both from schematic and the layout. All the simulation results from HSIPCE files show that all the requirements are satisfied.