Lab1: Design and Simulate a 2 Input CMOS NAND Gate
Submitter: Fei Xin
ID No.: 998095302
Date: 10/06/2000
In this lab, I designed a 2 input CMOS NAND gate layout by using Cadence. After extracting its corresponding circuit, I verified its logic function with HSPICE.
1. Layout
In the layout design, both NMOS and PMOS use the same size (w=12, L=2) under the 1.2um technology. I chose 20 mental1 for the VDD and GND. The two inputs were put on the top of the layout and output was on the bottom. The output used mental2. In addition, a N-well was used for the two PMOS transistors.
To see the layout, please click lab1-layout
2. Waveform
After getting the extraction with Cadence, I used Awaves to check
its logic result. First I added no load in the gate and got the right truth-table
listed below.
| in1 | in2 | out |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The related waveform can be seen by clicking lab1-withoutload-waveform
In addition, in order to test this gate's circuit performance, I added
a 0.1pF load on the output. Thus it brought delay time. Its waveform can
be seen in the lab1-load-waveform
and
I will analyse the delay in the 3rd section.
3. Circuit Simulation and delay analysis
Using Hspice and Awaves, I got the delay time
listed in the following table.
| both rising | both falling | one high, one rising | one high, one falling |
| pull-down | pull-up | pull-down | pull-up |
| Tphl | Tplh | Tphl | Tplh |
| 1.3 ns | 0.3 ns | 1.5 ns | 0.7 ns |
Consider the pull-up transition of the NAND gate. The worst-case scenario is activated when only a single PMOS transistor is turned on. Activating the second PMOS reduces the delay because the resistances are connected in parallel. The worst-case value of Tplh is about 0.7ns;
On the other hand, Tphl is about 1.3ns due to the two pull-down NMOS transistors are connected in series. The two resistances of NMOS are larger, thus the load capacitor needs much more time to discharge.
The result is reasonable but not very satisfied. I think one of the
reasons comes from the design process, the other reason is probably due
to the model that we used. I think the model is relatively too simple.
