DESIGN OF A NAND GATE
DAVID LAVIGNE
For a logical NAND gate the only time that a logical low value of zero would show up is if both the inputs were high at the same time. Other then that case a logical high value will show up, as you can see blow in my truth table with inputs A and B, and logical low and high values 0 and 1 respectively.2. NAND Schematic Image
2 INPUT NAND GATE TRUTH TABLE
A
B
OUT
0
0
1
0
1
1
1
0
1
1
1
0
To get the type of activity shown by the truth table I designed my two input NAND gate in the following way. It is known from the truth table that when either A or B has a logical low value the output will be high. In the case that either A or B (only one of them) is high while the other is low the value on the output will still be a high value, and if both A and B are high at the same time, the output is a logical low value.
Since the circuit operates in this way I place two PMOS transistors in parallel, which are tied to power. I also have the PMOS transistors connected to the output and the NMOS transistors. Since the PMOS transistors are connected this way if either A or B was to give a low signal it would let the current flow from the power supply to the output. The two NMOS transistors are connected in series, and are tied down to ground. Since the NMOS transistors are connected in series, the current is not sent to ground unless both A and B had high values. With my circuit set up in this way it works the way a NAND gate should, and below is a picture of the schematic I have for it.
From the simulation below you can see that the schematic I made does satisfy the truth table. I started off by having the values of A and B both 0 leaving the output with a value of 1. Following that I changed the value of B to 1, and left A at 0, which still yields an output of 1. Then I switched B back to 0, and switched A to 1, which still gave an output of 1. In the last case both A and B are 1, which changed the output from logical high to logical low. As you can see this simulation satisfies my schematic and truth table.
The first thing that I need to calculate in order to figure out the width of the NMOS and PMOS transistors for my NAND gate is to find out what the load capacitance is for it. In my case the load capacitance has to include the 32 CMOS inverters that are fanned out, and the 100fF of lumped capacitance. From there I start my calculations.
For my circuit the worst case of a FALLING transition on OUT occurs when B changes from a logical 0 to 1, while A is at 1. On the other hand the worst case of a RISING transition on OUT occurs when B changes from a logical 1 to 0, while A is at 1.
From the specifications given in the problem the values that I have for Wn = 0.36um, and Wp = 1.08um for the CMOS inverters. For the value of Cox I used the value given in the NOR gate example. Knowing that I can start plugging some values into an equation for the capacitance of an inverter, which is:
CINV = Cp + Cn
CINV = Cox * L * (Wn + Wp)
CINV = (6.03 fF/um^2) * (0.240 um) * (0.36 um + 1.08 um)
CINV = 2.08 fF
I just calculated the value for one inverter, but I need the value for all 32 inverters and the lumped wire capacitance to get the correct load.
Cload = 32 * CINV + 100 fF
Cload = 32 * 2.06fF + 100 fF
Cload = 166.6 fF
To determine the parasitic capacitances I want to look at the worst possible cases. For the NAND gate they are the same case which would give me a schematic like the one shown below of the worst case parasitic capacitance.
From this schematic it is clear to see where the parasitic capacitances come in to play. The capacitances for the PMOS transistors are CgdB, CgsB, CdbB, and CsbB, there are no capacitances for the other PMOS transistor. For the NMOS transistors there are CgdA, CdbA, CgsA, CsbA, CgdB, and CdbB. At this point I assume that the drain and source of each transistor are identical, so that each PMOS transistor is identical, and the same follows for the NMOS transistor. From this I get my equation for Cpara which is:
Cpara = 2*(Cgdo*Wp) + 2[Cj*Wp*Ls + Cjsw(2*Ls + Wp)] + 3*(Cgdo*Wn) + 3[Cj*Wn*Ls + Cjsw(2*Ls + Wn)]
Cpara = 2*(0.56 fF/um)(Wp) + 2[(1.88 fF/um^2)(Wp)(0.72um) + 0.37(2*0.72 + Wp)] + 3(0.63fF/um)(Wn) + 3[(1.92 fF/um^2)(Wn)(0.72um) + 0.44 fF/um^2(2*0.72 + Wn)]
Know that I have both the load capacitance and the parasitic capacitance; I can find the total capacitance. The total capacitance is found by adding the two capacitances that I just calculated. Therefore the equation looks like this:
Ctotal = Cload + Cpara
Ctotal = 166.6 fF + 4.57Wp + 7.36Wn + 2.966
Ctotal = 4.57Wp + 7.36Wn + 169.6fF
Since the switching has to be done within a certain time set in the specifications, I needed an equation that dealt with time. For that reason I used the following equation (dV = ½ Vdd):
I = Ctotal * dV/dt
I = (4.57Wp + 7.36Wn + 169.6fF) * (1.25V) / (300 ps)
I = 1.904E-5*Wp + 3.07E-5*Wn + 7.07E-4
Instead of calculating Wn the way it was done in the NOR gate example I calculated it another way. On page 134 of the textbook there is an equation for tpHL, which is:
tpHL = CL*VDD /(kn(Vdd-Vt)2)
From this equation I can calculate my Wn, because kn = k’ * (Wn/L). Like the example I will make the length twice as long for the NMOS transistor, since they are in series. Rearranging the equation I get:
Wn = 2*CL*VDD*L/(tpHL*k’*(VDD
– Vt)2)
Wn = 2*166.6fF*2.5*.24um/(250ps*275E-6*(2.5-.43)2)
Wn = 0.679um
I used 250 ps instead of 300 just to make sure that I was going to have my simulation run under 300 ps.
To calculate Wp I did just about the same thing that I did for Wn. Again on page 134 there is an equation for tpLHWp and it is: which involves
tpLH = CL*VDD/(kp(VDD
- |VT|)2)
In this case kp is equal to k’*(Wp/L). I plug that into the equation and I end up with the following equation:
Wp = CL*VDD*L/((tpLH *k’*(VDD - |VT|)2)
Wp = 166.6 fF * 2.5 * .24um/((250ps*96E-6*(2.5-.62)2)
Wp = 1.18um
Again I used the value of 250 ps to try to ensure that my circuit falls within the 300ps time limit.
5. Simulated vs. Hand Calculated Delays
tp is just the average of tpLH and tpHL.
| Hand Calculated Delays (in ps) |
Simulated Delays (in ps) |
|
| tp |
250 |
236 |
| tpLH |
250 |
206 |
| tpHL |
250 |
266 |
We also had to calculate both the Static and Dynamic Power of the gate. In the book it says that for CMOS inverter gates there is not static power comsumption, and that carries over to other CMOS gates. In my case there might be some, because PSTAT = Ileakage*VDD but it is a negligible amount of current. For the dynamic power: PDYNAMIC = PDYN + Pdp, and PDYN = CL*VDD2*f, while Pdp = VDD*Ipeak*f*(tr + tf)/2. To solve the dynamic power I first started with the PDYN part. PDYN = 166.6fF*2.52*1/500ps, and PDYN = .208 mW. The value of f was obtained by taking the reciprocal of the total propagtion delay.
To determine the value of Pdp I used the same values for VDD and f, but I had to calculate the rise and fall times which I did following the example on page 139 in the textbook. Changing around the equation and plugging in the numbers I got my rise time equal to my fall time which was 751ps. To find Ipeak, I calculated the saturation current for the PMOS transistor which came out to be .13mA. After plugging these values back into the Pdp equation I ended up with Pdp = 17.6uW. Adding up Pdp and PDYN I got the total dynamic power to be .226mW.
Below is a table of my comparisons:
| Hand Calculated (in mW) |
Simulated (in mW) |
|
| Static Power |
approximately 0 |
approximately 0 |
| Dynamic Power |
.226 |
0.222 |
6. Schematic Performance Verification
In the following image you can see that the tpLH time, and the tpHL time. The propagation delay times are circled in blue. tpLH is 206 ps and tpHL is 266 ps.
7. NAND Layout
Below is my NAND gate layout, with a total hieght of 140 lambda, and a total width of about 77.5 lambda.
8.
Layout Functional Simulation
On the graph below you can see the functionality from my NAND gate. I have outlined the regions, with red (A = B = 0), blue (A = 0, B = 1), green (A = 1, B = 0), and orange (A = 1, B = 1). You can see that during the first three cases (red, blue, and green) the output reamins high, but once it gets into the fourth region the output starts to decrease to a logical low value. According to this my NAND gate functions the way that it should.
9. Layout Performance Verification
In the following image you can see the actual performance of my NAND gate, which is well under the tpLH, and tpHL times.
In this lab I became very familiar with Microwind and DSCH2. I also created and simlated a functional NAND gate that met the specifications. I also noticed one reason why the numbers that I calculated were not the same as those from the simulation. When I would input a value for say the NMOS transistor width in microns, the exact value I put in was not produced. I notice this when I switched from lambda, and then back to microns. This is one of the reasons why my calculations were not exactly the same as the simulations.