**ANALYSIS
OF A RING OSCILLATOR BASED ON CHIP THERMAL SENSOR IN 65nm TECHNOLOGY**

**BASAB
DATTA, DHRUV KUMAR**

**VLSI
DESIGN PRINCIPLES (ECE 658) LAB 4 PROJECT**

**UNIVERSITY
OF MASSACHUSETTS-AMHERST**

**Email: bdatta@ecs.umass.edu,
dkumar@ecs.umass.edu **

**ABSTRACT**:

A ring oscillator’s delay dependence on
temperature gives a convenient way to measure temperature of a chip. Exhibiting
a linear dependence of oscillation frequency on junction temperature, this
simple circuit can be embedded inside any VLSI chip and in conjunction with a
counter it paves way for efficient and highly accurate temperature measurement.
We have analyzed a ring oscillator in 65 nanometer technology using the Berkeley
Predictive Technology Models and determined its frequency dependence on
temperature, supply voltage noise sensitivity, immunity to manufacturing
process variations using

**INTRODUCTION**:

The increase in circuit density and clock
speed has produced an increase in power consumption that has brought thermal
issues in the spotlight of VLSI design [1]. It has been reported that the
measured junction temperature of a 1-GHz 64-bit RISC processor implemented in
0.18 um technology is as high as 135 degrees Celsius at V_{dd}
= 1.9V, technology scaling makes this trend more severe and the junction
temperature of a 0.13 um CMOS chip has been estimated to be 3.2 times higher
than the junction temperature of a 0.35 um CMOS chip working under equivalent
conditions. The exponential increase in power density and hence, heat density
warrants a sustainable and reliable temperature detection mechanism which can
trigger the thermal management unit .Many thermal management techniques have
been developed at the architectural level like dynamic voltage scaling (DVS),
dynamic frequency scaling (DFS) etc[2]. All these techniques depend heavily on
an accurate circuit which can determine the on chip temperature. Once the thermal status of the chip is sensed
there are several ways to deal with the temperature problem, although all
solutions result in performance loss [2]. An accurate and detailed
identification of the thermal status of the processor is thus critical for the
selection of the most appropriate thermal management scheme and lies at the
heart of any temperature aware microarchitecture.

Another significant problem that needs to be
addressed is the leakage power variation with temperature in deep-submicron
technology. The leakage current in nanometer devices has increased drastically
due to reduction in threshold voltage, channel length and gate-oxide thickness.
There’s an added impact of an increasing number of modules in an IC that are
idle at any given time. In fact, 40% of the power consumed in Pentium 4 is due
to current leakage.

A number of CMOS temperature sensors have been
proposed which are very successful in accurately measuring temperature but most
are plagued with the common problem of being too large and power hungry thus
restricting their use across the circuit [4]. Diode based thermal sensors are
used for temperature detection in P4 processors and in the thermal sensor unit
of PowerPC processors [4]. The main advantage of the diodes as thermal
transducers is their low sensitivity to power supply noise. Unfortunately, in
cell-based design styles (where only digital gates are available) such sensors
are difficult to implement [1]. A crucial difference between PC Boards and
reconfigurable systems is that in the latter, the processing tasks are
dynamically distributed between several chips that change their functionality
at the hardware level. Thus, the detection of hotspots requires sensing the
temperature in each IC of the system [4]. Since microelectronic delays increase
with temperature, a way to measure chip heating is to construct an oscillator
and calibrate its output drift in MHz per degrees Celsius or Fahrenheit. This
establishes a natural link between temperature (an
analog magnitude) with digital chips through frequency. Hence a ring oscillator
is a good candidate for a thermal sensor. A ring oscillator consists of a
feedback loop that includes an odd number of inverters needed to produce the
phase shifting that maintains the oscillation (fig1)

**Fig 1:
An 11 stage ring oscillator.**

The
resulting period is twice the sum of the delays of all elements that compose
the loop.

T= 2 X N X t_{p}

f = 1/T

T
is the time period of oscillation and f is the frequency which depend on number
of inverters N and propagation delay of a single inverter in the chain, t_{p}.

Some
of the advantages of oscillators as thermal transducers are [4]:

1.
They can be easily implemented with few chip elements.

2.
The junction temperature is measured instead of the package temperature (like
other on-chip sensors)

3.
An array of sensors can be placed on the chip making possible the construction
of a thermal map of the die.

4.
The sensors can be dynamically inserted, moved or eliminated.

A
source of error in active thermal transducers is its own sensor dissipation.
However performing the measurements during a short enable window minimizes the
problem. The sensor’s capture counter must have enough precision to store the
temperature change during this measurement period.

**TEMPERATURE
MEASUREMENT**:

The
delay of any CMOS circuit depends on the temperature and hence it is expected
that the delay of a ring oscillator and hence its frequency will change as we
vary the temperature. Accordingly, at any given temperature, the oscillator
will exhibit a fixed frequency of oscillation.
By feeding these oscillations to a counter we obtain a convenient
measure of temperature related to the value of count after a fixed time. As
frequency of oscillations will reduce with temperature, so will the count value
and hence using a simple look up table, the processor can determine the
temperature and take appropriate action.

For
this scheme to work properly, it is essential that there is a linear variation
in the frequency with temperature.

To
test whether this is true, we constructed an 11 stage ring oscillator using 65 nm Berkeley Predictive Technology Models
with the following parameters:

Length
of channel = 65 nm

Width
of PMOS = 280.8 nm

Width
of NMOS = 93.6 nm

Supply
voltage Vdd = 0.8 volts

Our
analysis results for an 11 stage oscillator indeed confirm that the
relationship is strongly linear (fig 2).

**Fig** **2: The frequency
of ring oscillator is a linear function of on chip temperature**

Note
that we have analyzed the oscillator only from 20 degrees to 120 degrees
centigrade as that is the region of interest. For example, thermal throttling
of Pentium 4 starts at 60 degrees and the emergency reset occurs at 120
degrees. Thus, for all practical purposes, analyzing the oscillator in this temperature
window is safe. Further, this linear relationship is expected to continue for
temperatures exceeding 120 degrees as well, predicted by the following equation
which we determined from the analysis:

f = -5e+06(T) + 2e+09

Here
f is the frequency of oscillations and T is the on chip temperature.

Similar
results (fig 3) are obtained for different ratios of Wp to Wn, the channel
widths of PMOS to NMOS:

**Fig 3:
Oscillator is linear for all sizes of NMOS and PMOS**

As
seen in above plots, we can use different sizing for an oscillator without worrying
about the linearity in measurement. Further, note that there is not much change
in the absolute frequency at a given temperature for different sizes.

**IMMUNITY TO POWER
SUPPLY NOISE**:

To
test how the ring oscillator behaves when the supply voltage is changed, which
might be the case when there is noise in supply, we changed the Vdd voltage (from 0.6 to 1.0 volts) and observed that there
is a wide variation in measured frequency at a fixed temperature of 50 degrees
(fig 4).

**Fig 4: The frequency varies
widely as Vdd is changed**

The same trend of high sensitivity to power
supply noise is seen even if we change the Wp to Wn ratio, the ratio
of widths of PMOS to NMOS transistors. The following figures show our results
for various device sizes:

**Fig 5:
Device sizing does not reduce power supply noise sensitivity**

Thus we see that ring oscillator is extremely
sensitive to noise in supply voltage and it cannot be solved by device sizing
alone. This is in fact one of the demerits of a ring oscillator when used as a
thermal sensor.

**LEAKGE
POWER ESTIMATION**:

The dependence of
leakage power of a CMOS circuit as a function of temperature hints at the
possibility of measuring the leakage by using the embedded oscillator alone. Although there are
excellent leakage measurement tools available like Hotleakage,
they are useful only at the architectural level and further they are limited in
scope as they provide leakage only for cache style registers.

We feel that a ring oscillator can be used to
measure the leakage of an entire chip. For doing this we must know the number
of NAND, NOR and INVERTER gates in the design. As NAND and NOR are universal
gates, any design can be expressed as the suitable function of these gates.
Next, given a relationship between the frequency of oscillator and the leakage
of gates, we can determine the total leakage of the design.

To determine these relationships, we
constructed two input NAND and NOR gates and an Inverter in 65nm technology
using the standard sizing rules and obtained leakage as a function of actual
junction temperature. Next, we mapped this leakage to the frequency of
oscillation of ring oscillator which we earlier obtained (Wp : Wn
= 3:1). **Figure 6** shows our results:

**Fig 6 : Leakage of universal gates as a function of ring
oscillator frequency**

This means that once we break the design down
into a number of two input NAND and NOR gates and inverters, we can determine
the total leakage of the chip by measuring the frequency of oscillations. This
provides a means of direct measurement of leakage power and is valid for any
kind of circuit, whether combinational or sequential and is not limited to cache
style registers as in case of Hotleakage. Further this allows the designer to
work at the circuit level. A future work may be to further refine these models
and make models for other bigger circuits.

**SENSITIVITY
TO PROCESS PARAMETER VARIATIONS**:

Critical parameters of a MOSFET like effective
channel length, thickness of oxide, widths of metal interconnects etc vary with
inevitable variations in manufacturing process. This effect is more pronounced
for chips made in different batches than chips fabricated on the same wafer. In
all cases, we should make sure that the oscillator is immune to such
variations.

To model these effects, we did a

**Fig 7**

Similarly we obtained the following plots for
different sizing which show how the frequency deviates when the effective
length of a MOSFET changes **(fig 8)**:

**Fig 8**

We
calculated the average deviation from the nominal value of frequency in all
these cases and obtained the following results:

Wp:Wn |
Average deviation
(%) |

1 |
7.5 |

1.75 |
0.6 |

2.25 |
2.5 |

3 |
18.9 |

4 |
5.9 |

To a first order, it
looks like the optimal value of device ratio for maximum immunity to process
variations is around 1.75.

A further analysis to
see the dependence of average frequency deviation as a function of number of
stages was performed and similar results like fig 7 were obtained ( the sizing
was fixed at 3:1 ). Interestingly we observed a strong dependence on the number
of stages as seen in the following figure:

**Fig 9**

Thus it is seen that
to mitigate the effects of process variations, we must increase the number of
stages of a ring oscillator.

**POWER SUPPLY SENSITIVITY PROBLEM (REVISITED):**

From the results found
by us in the previous section we further explored whether we can make the
circuit more immune to power supply noise by increasing the number of stages.
This is a major problem as seen in figs 4 and 5 and it cannot be solved by
device sizing alone. By performing simulation at 50 degrees centigrade and a
fixed size of 3:1 for different number of stages, with increasing stages, we
obtained the following result:

**Fig 10**

We see that the slope
of frequency with power supply *decreases*
as the number of stages is increased.

This convincingly
shows that dependence of measured frequency on power supply variation is
reduced by increasing the number of stages. Or in other words, to make the
oscillator immune to power supply noise we must increase the number of stages.

**CONCLUSION**:

A ring oscillator is a
simple circuit and can be used as an on chip thermal sensor. It offers good
transducer characteristic of being linear in its measurement which is
independent of its sizing.

The estimation of
leakage power of a chip is possible given the number of universal gates and the
frequency of oscillations. One can use the empirical results and equations
which we have developed.

The process parameter
variations may be mitigated by increasing the number of stages of the
oscillator which also boosts the immunity to variations in power supply. In
general it is possible to make the oscillator immune to process variations and
supply noise by increasing the number of stages.

**POSSIBLE FUTURE WORK**:

Development of
suitable models to estimate the leakage power of different circuits as a
function of frequency of ring oscillator is one promising area of work. Further
analysis is warranted to quantify the dependence of deviation in frequency
measurement with the number of stages and the immunity of circuit to power
supply noise. Exploring the trade-offs in terms of power supply sensitivity and
process parameter variation when using different implementation styles for the
ring oscillator holds potential for future analysis.

**REFERENCES**:

[1]
– S. A. Bota, M. Rosales, J L Rossello,
J Seguara.” Smart temperature sensor for thermal testing
of Cell based

IC’s” IEEE Proceedings of the Design,
Automation and Test in Europe Conference and Exhibition,2005

[2] – Puyan Dadvar, Kevin Skadron. “Potential Thermal Security Risks” IEEE
Semiconductor and Thermal Symposium

2000.

[3] – Sergio Lopez-Buedo, Javier Garrido, Eduardo Boemo. “Thermal testing on reconfigurable computers” IEEE
design

and test of
computers” 2000.

[4] – Stefan Kaxiras, Polychronis Xekalakis. ”4T decay sensors: A new class of small, fast,
robust, and low-power,

Temperature/Leakage Sensors” ISLPED 2004.

**ACKNOWLEDGEMENTS**:

We thank Proff. Wayne Burleson, Sheng Xu and Jinwook Jang for their guidance in our little
endeavor.