module pll (u1, u2, ID_clock, reset);

parameter M  = 32;	
parameter K  =  8;			
parameter N  = 16;
parameter PHASE_DETECTOR_SELECT = 1;	// 1 for xor, 2 for JK FF	


parameter M2 = 5;	// log base 2 of M
parameter K2 = 3;	// log base 2 of K
parameter N2 = 4;	// log base 2 of N


input  u1, ID_clock, reset;
output u2;
wire reset, XOR_out, JK_out, DN_UP, K_clock, u2, u2_prime;
reg [(K2-1):0] Kup, Kdn;
reg Carry, Borrow, Toggle_FF, Carry_pulse, Borrow_pulse, advanced, delayed;
reg ID_out, ID_out_2, ID_out_4, ID_out_8, ID_out_16;
reg Carry_new, Borrow_new;

assign K_clock = ID_clock;

jk jk1(.Q (JK_out), .J (u1), .K (u2_prime) );
assign XOR_out = u1 ^ u2_prime;

assign DN_UP = PHASE_DETECTOR_SELECT ? XOR_out : JK_out;


//*****KCounter****//

always@(negedge K_clock or negedge reset)
begin
if(!reset)
 begin
 Kup <= 0;
 Kdn <= 0;
 Carry <= 0;
 Borrow <= 0;
 end
else 
  begin
  if(DN_UP) Kdn <= Kdn + 1;
  else Kup <= Kup + 1;
  Carry  <= Kup[K2-1];
  Borrow <= Kdn[K2-1];
  end
end


//***ID Counter*****//
//always@(posedge Carry or posedge ID_clock)
always@(posedge ID_clock)
begin
 if(!Carry) 
   begin
   Carry_new <= 1;
   Carry_pulse <= 0;
   end
 else if(Carry_pulse) 
   begin
   Carry_pulse <= 0;
   Carry_new <= 0;
   end
 else if(Carry && Carry_new) 
   begin
   Carry_pulse <= 1;
   Carry_new <= 0;
   end
 else 
   begin 
   Carry_pulse <= 0;
   Carry_new <= 0;
   end
 
 //if(ID_clock) Carry_pulse <= 0;
 //else Carry_pulse <= 1;
end

//always@(posedge Borrow or posedge ID_clock)
always@(posedge ID_clock)
begin
  if(!Borrow) 
    begin
    Borrow_new <= 1;
    Borrow_pulse <= 0;
    end
  else if(Borrow_pulse) 
    begin
    Borrow_pulse <= 0;
    Borrow_new <= 0;
    end
  else if (Borrow && Borrow_new) 
    begin
    Borrow_pulse <= 1;
    Borrow_new <= 0;
    end
  else 
    begin
    Borrow_pulse <= 0;
    Borrow_new <= 0;
    end


// if(ID_clock) Borrow_pulse <= 0;
// else Borrow_pulse <= 1;
end

always@(posedge ID_clock or negedge reset)
begin
 if(!reset) 
   begin
   Toggle_FF <= 0;
   delayed <= 1;
   advanced <= 1;
   end
 else 
   begin
   if(Carry_pulse) 
     begin
     advanced <= 1;
     Toggle_FF <= !Toggle_FF;
     end
   else if(Borrow_pulse) 
     begin
     delayed <= 1;
     Toggle_FF <= !Toggle_FF;
     end
   else if(Toggle_FF == 0)
     begin
     if(!advanced) Toggle_FF <= !Toggle_FF;
     else if(advanced)
       begin
       Toggle_FF <= Toggle_FF;
       advanced <= 0;
       end
     end
   else
     begin
     if(!delayed) Toggle_FF <= !Toggle_FF;
     else if(delayed)
       begin
       Toggle_FF <= Toggle_FF;
       delayed <= 0;
       end 
     end  
  end
end

//always@(ID_clock)
always@(ID_clock or Toggle_FF)
begin
 if(Toggle_FF) ID_out <= 0;
 else
  begin
  if(ID_clock) ID_out <= 0;
  else ID_out <= 1;
  end
end

assign u2 = ID_out;

//***NCounter***//
always@(negedge ID_out or negedge reset)
begin
 if(!reset) ID_out_2 <= 0;
 else ID_out_2 <= !ID_out_2;
end

always@(negedge ID_out_2 or negedge reset)
begin
 if(!reset) ID_out_4 <= 0;
 else ID_out_4 <= !ID_out_4;
end

always@(negedge ID_out_4 or negedge reset)
begin
 if(!reset) ID_out_8 <= 0;
 else ID_out_8 <= !ID_out_8;
end

always@(negedge ID_out_8 or negedge reset)
begin
 if(!reset) ID_out_16 <= 0;
 else ID_out_16 <= !ID_out_16;
end

assign u2_prime = ID_out_8;

endmodule


/////////////////////////////////

module jk (Q, J, K);
input J, K;
output Q;
reg Q;

always@(posedge J)
begin
	if(K==1)	Q <= !Q;
	else		Q <= 1;
end
always@(posedge K)
begin
	if(J==1)	Q <= !Q;
	else		Q <= 0;
end

/*
always@(posedge J or posedge K)
begin
	if(J==1)
	begin
	  if(K==0)	Q <= 1;
	  else		Q <= !Q;
	end
	else
	begin
	  if(K==0)	Q <= Q;
	  else		Q <= 0;
	end
	
	if((J==0)&&(K==0)) 		Q <=  Q;
	else if((J==0)&&(K==1))		Q <=  0;
	else if((J==1)&&(K==0))		Q <=  1;
	else 				Q <= !Q;
	
end	
*/
endmodule