The all-digital phase-locked loop (ADPLL)

Two ADPLLs have been designed at the RTL level using Verilog HDL and synthesized with the Virginia Tech VTVT library. The gate-level netlist has been verified for functionality using Cadence Verilog-XL and a stimulus file. Both ADPLL designs were taken from the following text, which is an invaluable PLL reference:

R. E. Best. Phase-Locked Loops Design Simulation and Applications. The McGraw-Hill Companies, New York, New York, 1999.

The first design is represented by the block diagram below: Block Diagram

Best's book goes on to display the correct waveforms for this PLL: Book Waveforms

As mentioned, this PLL has been verified at the gate-level. The corresponding waveforms from my design, as viewed by Cadence Verilog-XL, are displayed below: My Waveforms

In addition, my RTL code is provided here: My code

A second pll is has also been designed. Its block diagram is below.

Block Diagram

Best's book goes on to display the correct waveforms for this PLL: Book Waveforms

As mentioned, this PLL has been verified at the gate-level. The corresponding waveforms from my design, as viewed by Cadence Verilog-XL, are displayed below: My Waveforms

In addition, my RTL code is provided here: My code