VLSI DESIGN PRINCIPLES (658)

 

Lab Assignment 1

 

DANAI CHASAKI 

ID: 22169216

 

 

Objective: Design a CMOS 2-input nand gate

 

 

POST: Truth Table

 

 

NAND  Gate

 

A

B

F

0

0

1

0

1

1

1

0

1

1

1

0

 

POST: Image of your schematic

 

In order to draw the schematic which implements the truth table we used the schematic editor of Cadence (icms&). We chose the nmos, pmos devices and supply nets from the library NCSU_Analog_Parts.

The NAND gate consists of 2 PMOS transistors in parallel and 2 NMOS transistors in series. The screen image of the schematic is shown below:

 

 

 

POST: Image of simulator output

 

The next step is to extract the netlist file of our schematic in Cadence. After this we are able to find a file called netlist in the nand directory that we have created. Now what we have to do is to convert the netlist file to one compatible with IRSIM. So we run the perl code schm2sim.pl located in our sim directory. The output is created in sch.sim and we are ready to run the IRSIM tool.

The output is shown below:

 

POST: Hand Calculations

 

 

 

First we identify the worst-case transitions. The worst case FALLING transition on OUT occurs when there is a RISING edge on B while A is held constant at logic 1.
(10 -> 11)

The worst case RISING transition on OUT occurs when there is a FALLING edge on B while A is held constant at logic 1.

(11 -> 10 , due to the intermediate capacitance that exists between the 2 NMOS transistors we have the worst case rising transition when A is on and B is off)

 

Now we determine the load capacitance Cload.

We are able to drive 32 minimum size inverters plus 100 fF of lumped wire capacitance.

Then:

Cinv = Cp + Cn

Cinv = Cox * L * (Wn + Wp)

Cinv = (6.03 fF/um^2) * (0.24 um) * (0.3 um + 0.9 um)

Cinv = 1.73664 fF

 

Cload = 32 * Cinv + 100 fF

Cload = 16 * (2.08 fF) + 100 fF

Cload = 155.57 fF

 

Next we determine the parasitic capacitance Cpara.

In the equations below the subscripts indicate the transistor and terminals. For example, in CgdnA, "gd" indicates the capacitor between the gate and drain terminals and "nA" indicates it's the NMOS transistor whose gate is connected to input A.

 

Looking at the schamtic above and taking into consideration all the parasitic capacitancies of the circuit we have :

 

C = CgdnA + CdbnA + CgsnA + CsbnA + CgdnB + CdbnB + CgdpA + CdbpA + CgdpB + CdbpB

 

We will assume that the drain and source of each transistor is geometrically identical, the two PMOS transistors are identical, and the two NMOS transistors are identical.

 

Cpara = 2*Cgdp + 2*Cdbp + 3*Cgdn + 3*Cdbn

 

Cpara = 2*(Cgdo*Wp) + 2*[Cj*Wp*Ls + Cjsw(2*Ls+Wp)]

        + 3*(Cgdo*Wn) + 3*[Cj*Wn*Ls + Cjsw(2*Ls+Wn)]

 

Cpara = 2*(0.56 fF/um)(Wp) + 2*[(1.88 fF/um^2)(Wp)(0.72 um) + (0.37 fF/um^2)(2*(0.72 um) + Wp)]

        + 3*(0.63 fF/um)(Wn) + 3*[(1.92 fF/um^2)(Wn)(0.72 um) + (0.44 fF/um)(2*(0.72 um) + Wn)]

 

Cpara = 4.5672*Wp + 7.3572*Wn + 2.9664

 

Now we compute Ctotal, the sum of Cload and Cpara.

 

Ctotal = Cpara + Cload

 

Ctotal = 4.57*Wp + 7.36*Wn + 2.97 + 155.57

Ctotal = 4.57*Wp + 7.36*Wn + 158.54 fF

Then we compute the total current required to switch all of this capacitance by 1/2 Vdd (= 1.25 V) in the 300 ps.

 

I = Ctotal * dV/dt

 

I = (4.57*Wp + 7.36*Wn + 158.54 fF) * (1.25 V) / (300 ps)

 

I = 1.904E-5*Wp + 3.07E-5*Wn +66.05E-5

 

Assuming operation in the saturation region we compute the current in the NMOS transistors (We double the channel length because we're modeling them as two resistors in series).Then we set this current equal to the capacitor current.

 

I = 0.5 * kn' * (Wn /2 L) * (Vgs - Vt)^2

I = 0.5 * (275E-6) * (Wn / 0.48 um) * (2.5 - 0.43)^2

I = 1.227E-3*Wn

 

1.904E-5*Wp + 3.07E-5*Wn +66.05E-5 = 1.227E-3*Wn

 

1.12E-3*Wn - 1.9E-5*Wp =66.05E-5

 

Then we compute the current in the PMOS transistors and we set this current equal to the capacitor current.

I = 0.5 * kp' * (Wp / L) * (Vgs - Vt)^2

I = 0.5 * (96E-6) * (Wp / 0.24 um) * (2.5 - 0.62)^2

I = 7.068E-4*Wp

 

1.904E-5*Wp + 3.07E-5*Wn +66.05E-5 = 7.068E-4*Wp

 

-1.9E-5*Wp + 1.12E-3*Wn = 66.05E-5

 

Now we solve the two equations for Wn and Wp.

 

Wp = (66.05*E-5 + 3.07E-5*Wn) / 6.877*E-4

Wp = 0.9604 + 0.044*Wn

 

-1.9E-5(= 0.9604 + 0.044*Wn ) + 1.12*E-3*Wn = 66.05*E-5

 

Wn = 67.87/1.12E-3 = 0.605 um

 

Wp = 0.9604 + 0.044* 0.605 = 0.987 um

 

 

Having the values of Wn and Wp we can compute the propagation delay as follows:

 

Tplh = 0.69*Rp*Cload

 

Where Rp is approximately 31Kᾨ when W/L = 1

 

Thus Tplh = 0.69 * 31K*156fF/(987/240)

 

Tplh = 811.38 ps

 

Tphl = 0.69*2*Rn*Cload

 

Where Rn is approximately 13 Kᾨ when W/L=1

 

Thus Tphl = 0.69*2*13k*156 fF/ (605/240)

 

Tphl = 1110.20ps

 

Tp = (Tplh + Tphl) /2 = 960.79 ps

 

In order to determine the power dissipation we have to compute both static and dynamic power.

  

Static power dissipation: Pstatic = Istat * Vdd = Istat * 2.5

 

Istat is equal to drain area * 100 pA/um^2. (The leakage current per unit drain area is usually approximately 100 pA/um^2)  

 

We can compute the drain area of nmos and pmos as follows:

 

Drain area (nmos)= Wn*Ls = 1.92*0.72 = 1.38 um^2

Drain area (pmos)= Wp*Ls = 2.88*0.72 = 2.07 um^2

 

Pstatic (nmos) = 2.5*(100*10e-12*1.38) = 50.4 pW

Pstatic (pmos) = 2.5*(100*10e-12*2.07) = 34.5 pW

 

Dynamic power dissipation: Pdyn = Cload*Vdd^2 /(Propagation delay)

            = 155.57fF * 2.5*2.5 / 300ps

            = 3.24mW

 

POST: Simulation waveforms with performance metrics annotated

POST: A table comparing tPHL, tPLH, tP, PSTAT and PDYN for the analytical model and the simulation

 

In this step we simulate the design using HSPICE in order to verify its performance. We use first the perl script schm2spice.pl to convert our netlist into true spice format. Then we create a nand.spice file and we run it.

Using the tool awaves we get the following results:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

We now zoom in the Low to high transition

 

 

 

 

 

Zooming in the high to low transition we have :

 

 

 

The performance metrics of our design appear in the file nand.mt0

 

$DATA1 SOURCE='HSPICE' VERSION='W-2005.03-SP1   '

.TITLE '************************** nand gate *****************************'

pavghl             pavglh               tphl                tplh

temper             alter#

 

2.810e-06        3.252e-05        2.152e-09        1.440e-10

25.0000           1.0000

 

We can see that both tphl, tplh < 300 ps . So we don’t need to modify the transistor sizes to slow down the gate.

 

The results from the analytical model are shown here:

 

 

tphl

tplh

tp

Pstatic

Pdyn

analytical

1110.20 ps

811.38 ps

960.79 ps

84.9 mW

3.24 mW

 

 

 

 

POST: An image of your layout, with the total height and width annotated

 

 

 

The height and width computed using the ruler in the layout are:

 

Height: 15.16

Width: 6.78

 

Thus we have approximately:

 

Total Height= 15.16 /0.12 = 126 lambda

Total Width = 6.78/ 0.12= 56 lambda

 

 

 

 

 

 

 

 

 

 

POST: Image of simulator output

 

In the same way as before we extract the schematic netlist from our design, then convert it to a file compatible with IRSIM and run the simulation. The output shows that the gate has the right functionality.