.options sda=2

$****************************************************************************
$ Hspice Netlist:
$ Block: /user5/alaffely/cell_design/ROD/add_accum/extracted/layout.cdb
$ Netlist Time: Oct 30 00:13:52 2000
$****************************************************************************


$****************************************************************************
$ MODEL Declarations
$****************************************************************************
.model nfet nmos level=2 vto=0.7 gamma=0.2 kp=3e-05 lambda=0.02 tox=6e-07
.model pfet pmos level=2 vto=-0.7 gamma=0.4 kp=1.5e-05 lambda=0.03 tox=6e-07


$****************************************************************************
$ Main Circuit Netlist:
$
$ Block: add_accum
$ Last Time Saved: Oct 30 00:11:46 2000
$****************************************************************************

$carry out generation

mx34 cout_b phi vdd vdd pfet w=3u l=1u

mx18 yes_cin a phi_gnd gnd nfet w=3u l=1u
mx17 phi_gnd b yes_cin gnd nfet w=3u l=1u
mx16 yes_cin carry_in cout_b gnd nfet w=3u l=1u
mx14 gnd phi phi_gnd gnd nfet w=3u l=1u
mx13 phi_gnd a n24 gnd nfet w=3u l=1u
mx12 n24 b cout_b gnd nfet w=3u l=1u

mx36 carry_out cout_b n30 vdd pfet w=6u l=1u
mx35 n30 rst vdd vdd pfet w=6u l=1u

mx20 carry_out cout_b gnd gnd nfet w=1u l=1u
mx19 carry_out rst gnd gnd nfet w=1u l=1u
ccout carry_out gnd .01pf

$Summation

mx27 sum_b cout_b no_carry_p vdd pfet w=6u l=1u
mx26 no_carry_p carry_in vdd vdd pfet w=6u l=1u
mx25 vdd b no_carry_p vdd pfet w=6u l=1u
mx24 no_carry_p a vdd vdd pfet w=6u l=1u

mx30 sum_b carry_in n29 vdd pfet w=9u l=1u
mx29 n29 b n28 vdd pfet w=9u l=1u
mx28 n28 a vdd vdd pfet w=9u l=1u

mx4 gnd a no_carry_n gnd nfet w=2u l=1u
mx3 no_carry_n b gnd gnd nfet w=2u l=1u
mx2 gnd carry_in no_carry_n gnd nfet w=2u l=1u
mx1 no_carry_n cout_b sum_b gnd nfet w=2u l=1u

mx9 gnd a n22 gnd nfet w=3u l=1u
mx8 n22 b n21 gnd nfet w=3u l=1u
mx7 n21 carry_in sum_b gnd nfet w=3u l=1u

mx21 vdd sum_b sum_a vdd pfet w=3u l=1u
mx0 sum_a sum_b gnd gnd nfet w=1u l=1u


$Register

mx23 vdd sum_a n25 vdd pfet w=6u l=1u
mx22 n25 phib reg vdd pfet w=6u l=1u

mx6 reg phi n20 gnd nfet w=2u l=1u
mx5 n20 sum_a gnd gnd nfet w=2u l=1u

mx33 vdd rst n27 vdd pfet w=18u l=1u
mx32 n27 phi n26 vdd pfet w=18u l=1u
mx31 n26 reg sum vdd pfet w=18u l=1u

mx15 gnd rst sum gnd nfet w=4u l=1u
mx11 sum phib n23 gnd nfet w=4u l=1u
mx10 n23 reg gnd gnd nfet w=4u l=1u

csum sum gnd .05pf

** Fixed voltages
Vdd vdd gnd dc 5.0
Vb b sum dc 0 
Vphi phi gnd dc 0 pulse (0 5 4n 1n 1n 4n 10.0n)
Vphib phib gnd dc 0 pulse (5 0 4n 1n 1n 4n 10.0n)

**Varying Voltages
Va a gnd dc 0 pulse (0 5 13n 1n 1n 9n 20.0n)
Vcin carry_in gnd dc 0
Vrst rst gnd dc 0 pulse (5 0 1.0n 1n 1n 95.0n 120.0n)


.options list node post


.tran 0.03ns 120.0ns
.end